FPGA CW Keyer (8)

Sending an internally stored message.

    always @ (message_state) begin
        case(message_state)
            5'b00000: begin message_text <= 16'b1110_1011_1010_0011; end
            5'b00001: begin message_text <= 16'b1011_1010_1110_0000; end
//
        endcase
    end

The pattern for the key output signal is directly encoded in 16-bit words.