Keep synthesis is a Verilog HDL synthesis attribute. You can use this attribute to keep a combinational node so you can observe the node with the SignalTap II Logic Analyzer.
wire get_now /* synthesis keep */ ;
wire get_word /* synthesis keep */ ;
assign get_now = (async_count == 7'h9 || async_count == 7'h11 || async_count == 7'h19
|| async_count == 7'h21 || async_count == 7'h29 || async_count == 7'h31
|| async_count == 7'h39 || async_count == 7'h41 )? 1'b1 : 1'b0;
assign get_word = (idle1 == 1'b1 && idle2 == 1'b0)? 1'b1 : 1'b0;
Other usefull attributes are: /* synthesis noprune */, and /* synthesis preserve */ for registers.
http://quartushelp.altera.com/15.0/mergedProjects/hdl/vlog/vlog_file_dir.htm