FPGA – Page 4 – Spinor Lab

May 21, 2016

FPGA CW Keyer (6)

Doing dash and dot keying.

Input pins,IN_DASH and IN_DOT, are pulled-up internally.

May 19, 2016

FPGA CW Keyer (5)

The waveform of the KEY output signal from the FPGA board while squeezing.

May 18, 2016

Can’t resolve multiple constant drivers

This is something I felt uneasy in FPGA CW Keyer (4) when I added dot and dash memories.

May 14, 2016

FPGA Evaluation Kit (3)

Receiving DC power (+5V) via USB I/F is somewhat complicated due to various standard and custom protocols employed. Sometimes D+ and D- lines are used to convey information.

https://www.maximintegrated.com/en/app-notes/index.mvp/id/5801

http://www.ti.com/lit/ds/symlink/tps2540a.pdf

This causes a problem with the PIC board, MAX10-JB, because some of the I/O pins of the PIC microcontroller are used both for D+ and D- lines for USB I/F, and for writing into its flash program memory.

To avoid interference, I pulled off the USB cable and used an external power supply just while programming the flash memory.

The green flushing LED on the FPGA evaluation board, MAX10-FB, shows that the flash memory was successfully programmed and the verification was OK.

May 13, 2016

Recommended Practices (2)

Here is an HDL design example given by Altera.

https://www.altera.co.jp/support/support-resources/design-examples/design-software/verilog/ver-state-machine.html

// 4-State Moore state machine

// A Moore machine's outputs are dependent only on the current state.
// The output is written only when the state changes.  (State
// transitions are synchronous.)

module moore_mac
(
	input	clk, data_in, reset,
	output reg [1:0] data_out
);
	
	// Declare state register
	reg		[1:0]state;
	
	// Declare states
	parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;
	
	// Output depends only on the state
	always @ (state) begin
		case (state)
			S0:
				data_out = 2'b01;
			S1:
				data_out = 2'b10;
			S2:
				data_out = 2'b11;
			S3:
				data_out = 2'b00;
			default:
				data_out = 2'b00;
		endcase
	end
	
	// Determine the next state
	always @ (posedge clk or posedge reset) begin
		if (reset)
			state &lt;= S0;
		else
			case (state)
				S0:
					state &lt;= S1;
				S1:
					if (data_in)
						state &lt;= S2;
					else
						state &lt;= S1;
				S2:
					if (data_in)
						state &lt;= S3;
					else
						state &lt;= S1;
				S3:
					if (data_in)
						state &lt;= S2;
					else
						state &lt;= S3;
			endcase
	end
	
endmodule

You can copy and paste such example codes, or can insert the code from a template if you are using Quartus Prime.

May 12, 2016

FPGA Evaluation Kit (2)

A PIC board, MAX10-JB, is plugged on top of the FPGA evaluation board, MAX10-FB. A bright white LED is flushing to indicate that the pre-mounted FPGA is working fine with a pre-programmed configuration.

The PIC board works like an Altera’s USB-Blaster Download Cable.

May 11, 2016

Recommended Practices

https://www.altera.com/en_US/pdfs/literature/hb/qts/qts-qps-handbook.pdf

There are recommended practices in almost everything.

For example, The ARRL Operating Manual says that “When replying to a CQ, give both call signs clearly — yours and the CQing station.”

So I am now learning recommended design practices and coding styles for FPGAs. Of course, the practices differ a lot depending on the devices you use and the development tools employed.

May 10, 2016

FPGA Evaluation Kit

Various kinds of evaluation kits are available. This board is from Altera and looks very nice with on-board HDMI output capability.
https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-max-10m50-evaluation.html

Here is the board I am going to use. An FPGA, Altera’s MAX 10 (10M08SAE144C8G), is pre-mounted, but you need to solder other parts, such as a 256kbit SDRAM, and a 48MHz Xtal oscillator.

More detailed description of the board is here.
(No, I don’t think they have pages written in English.)

Tag: FPGA

FPGA CW Keyer (7)