FPGA CW Keyer (3)

次は、ダッシュのみです。

    reg[1:0] r_dash; 
    wire     w_dash; 

//---------- generate dash ---------------------
    always @ ( posedge CLK or negedge RST_N) begin
        if ( RST_N == 1'b0 ) begin 
            r_dash <= 2'h0;
        end     
        else if ( IN_DASH == 1'b0 || r_dash != 2'h0 ) begin 
            if ( r_dash == 2'h3 ) begin 
                r_dash <= 2'h0;
            end     
            else begin
                r_dash <= r_dash + 2'h1; 
            end     
        end     
        else begin
            r_dash <= 2'h0;
        end     
    end

//---------- w_dash ----------------------------

    assign w_dash = ( r_dash == 2'h0 ) ? 1'b0 : 1'b1;