FPGA CW Keyer (2)

最初はドットのみでシミュレーションします。いつも言うことですが、細かい部分は気にしないで下さい。

//---------  test bench ---------------------
initial begin
    CLK <= 1'b1;
    forever begin
        #10;
        CLK <= ~CLK;
    end
end

initial begin
    RST_N <= 1'b0;
     #50;
    RST_N <= 1'b1;
    #1100000;
    $finish;
end

initial begin
    IN_DOT <= 1'b1; #125; 
    IN_DOT <= 1'b0; #10;
    IN_DOT <= 1'b1; #100;
    IN_DOT <= 1'b0; #30;
    IN_DOT <= 1'b1; #100;
    IN_DOT <= 1'b0; #60;
    IN_DOT <= 1'b1; #100;
    IN_DOT <= 1'b0; #80;
    IN_DOT <= 1'b1; #100;
    IN_DOT <= 1'b0; #100;
    IN_DOT <= 1'b1; #1000000;
end

//---------  generate dot ---------------------
    always @ (posedge CLK or negedge RST_N) begin
        if ( RST_N == 1'b0 ) begin
            r_dot <= 1'b0;
        end
        else if ( IN_DOT == 1'b0 ) begin
            r_dot <= ~r_dot;
        end
        else begin
            r_dot <= 1'b0;
        end
    end